Code: BIE-APS.21 Architectures of Computer Systems
Lecturer: prof. Ing. Pavel Tvrdík CSc. Weekly load: 2P+2C Completion: A, EX
Department: 18104 Credits: 5 Semester: W
Description:
Students will learn the construction principles of internal architecture of computers with universal processors at the level of machine instructions. Special emphasis is given on the pipelined instruction processing and on the memory hierarchy. Students will understand the basic concepts of RISC and CISC architectures and the principles of instruction processing not only in scalar processors, but also in superscalar processors that can execute multiple instructions in one cycle, while ensuring the correctness of the sequential model of the program. The course further elaborates the principles and architectures of shared memory multiprocessor and multicore systems and the memory coherence and consistency in such systems.
Contents:
1. Quantitative principles of computer design, Amdahl?s law, computer performance evaluation, benchmarks.
2. Instruction set architectures: taxonomy RISC processors vs. CISC processors, assembly language.
3. Verilog as a hardware description language: syntax and semantics.
4. Incremental design of a single-cycle RISC processor, principles and basic implementations of CPU control units.
5. Design of a simple pipelined RISC processor, hazards in the pipeline and their elimination.
6. Memory hierarchy: Cache memory principle, various implementations (direct-mapped, fully associative, N-way set-associative).
7. Memory hierarchy: Virtual memory (paging) and its HW support in memory management units of conventional CPUs.
8. Multicore CPUs and multiprocessor systems. Cache memory coherence, the MESI protocol, directory-based coherence.
10. Memory consistency and the sequential consistency model. Synchronization instructions for accessing shared memory.
11. Superscalar CPUs I: Introduction to instruction-level parallelism. Static (in-order) and dynamic (out-of-order) instruction execution, register renaming (Tomasulo's algorithm).
12. Superscalar CPUs II: Memory-referencing instructions, load bypassing and load forwarding, speculative loads from memory. Memory consistency for multi-core CPUs.
13. Superscalar CPUs III: Branch prediction, speculative instruction prefetching and execution.
Seminar contents:
1. Evaluation of computer performance
2. ISA and the MIPS assembly language
3. Programming in assembly language for MIPS
4. Hardware description language (Verilog)
5. Basic components of simple RISC processors
6. Pipelined processor
7. Cache memory viewed by CPU/assembler
8. Cache memory viewed by a C/C++ programmer
9. MESI coherence protocol
10. Memory consistency and synchronization primitives
11. Memory consistency viewed by a C/C++ programmer
12. Superscalar processors
13. Semestral projects check, assessment
Recommended literature:
1. Patterson D. A., Hennessy J. L. : Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2014. ISBN 978-0128012857.
2. Hennessy J.L., Patterson D.A. : Computer Architecture: A Quantitative Approach (6th Edition). Morgan Kaufmann, 2017. ISBN 978-0128119051.
3. Shen J. P., Lipasti M. H. : Modern Processor Design. Fundamentals of Superscalar Processors. Waveland Press, 2013. ISBN 978-1478607830.
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