Description:

Aim of the course is to acquaint the students with principles of digital circuit simulation at RTL (Register Transfer Level) and TLM (Transaction Level Modeling) levels and with the properties of proper tools. The course covers today recent verification methods, too.

Contents:

1. Fundamental simulation and verification principles.
2. Simulation languages VHDL and Verilog.
3. Sequential and paralel simulation environment.
4. Hierarchical structure specification, parametrization.
5. Functions, procedures, and events in simulation models.
6. Design checking, using of assertions.
7. Verilog/SystemVerilog: introduction, data types, comparisons.
8. Communication between modules, transactions.
9. Simulation management, random and delimited stimulus generation, coverage control.
10. Advanced design control in simulation, assertion in SystemVerilog.
11. Universal Verification Methodology (UVM).
12. Advanced constructions, register model.

Seminar contents:

1. Introduction, VHDL/Verilog project - Assignment.
2. VHDL/Verilog project - Consultation.
3. VHDL/Verilog project - Evaluation.
4. Test 1 - VHDL/Verilog, Verilog/SystemVerilog project - Assignment.
5. Verilog/SystemVerilog project - Consultation.
6. Test 2 - Verilog/SystemVerilog, Verilog/SystemVerilog project - Evaluation.

Recommended literature:

1. Mehta, A. B.: SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications. Springer, 2016. ISBN 9783319305394.
2. Mehta, A. B.: ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies. Springer, 2018. ISBN 9783319594187.
3. Mehler, R.: Digital Integrated Circuit Design Using Verilog and Systemverilog (1st Edition). Elsevier, 2014. ISBN 9780124095298.
4. Cohen, B. - Kumari, S. V. A. - Piper, L.: SystemVerilog Assertions Handbook (3rd Edition). VhdlCohen Publishing, 2013. ISBN 978-0-9705394-3-6.

Keywords:

Module, interface, signal, delta delay, resolution function, inertial and transport delay, sequential environment, parallel environment, behavioral description, structural description, transaction level modeling, assertions, parallel simulation.

Abbreviations used:

Semester:

• W ... winter semester (usually October - February)
• S ... spring semester (usually March - June)
• W,S ... both semesters

Mode of completion of the course:

• A ... Assessment (no grade is given to this course but credits are awarded. You will receive only P (Passed) of F (Failed) and number of credits)
• GA ... Graded Assessment (a grade is awarded for this course)
• EX ... Examination (a grade is awarded for this course)
• A, EX ... Examination (the award of Assessment is a precondition for taking the Examination in the given subject, a grade is awarded for this course)

Weekly load (hours per week):

• P ... lecture
• C ... seminar
• L ... laboratory
• R ... proseminar
• S ... seminar